Stack: Fast, automatic memory for local variables. Limited size, LIFO order. Risk of stack overflow in deep recursion.

Heap: Dynamic memory allocation via malloc/new. Slower, fragmentation risk. Avoid in hard real-time systems due to unpredictable allocation time.

Volatile prevents compiler optimization that assumes variable doesn't change unexpectedly.

Use cases: Hardware registers, interrupt service routine variables, memory-mapped I/O, variables modified by multiple threads/interrupts.

• Flash: Non-volatile program memory, slower write, limited erase cycles
• SRAM: Volatile data memory, fast access, limited size
• EEPROM: Non-volatile data storage, byte-wise access, very limited writes
• Registers: Fastest access, control peripheral functions

Memory alignment ensures data is stored at addresses divisible by the data size (e.g., 4-byte int at address divisible by 4).

Benefits: Faster access, prevents crashes on some architectures. Compiler adds padding to structs for alignment.

typedef struct {
    uint8_t buffer[BUFFER_SIZE];
    uint16_t head;
    uint16_t tail;
    bool full;
} circular_buffer_t;

bool cb_put(circular_buffer_t *cb, uint8_t data) {
    if (cb->full) return false;
    cb->buffer[cb->head] = data;
    cb->head = (cb->head + 1) % BUFFER_SIZE;
    cb->full = (cb->head == cb->tail);
    return true;
}

Function pointers store addresses of functions, enabling dynamic function calls.

Use cases: State machines, callback functions, interrupt vector tables, polymorphism in C. Example: `void (*callback)(int) = &my_function;`

• Set bit: `reg |= (1 << n)`
• Clear bit: `reg &= ~(1 << n)`
• Toggle bit: `reg ^= (1 << n)`
• Check bit: `if (reg & (1 << n))`
• Mask multiple bits: `reg |= 0x0F` (set lower 4 bits)

#define: Preprocessor replacement, no type checking, no memory allocated, good for hardware register addresses.

const: Type-safe constant, allocated memory, better for arrays and complex data. Use const for values, #define for addresses.

Microcontroller: CPU, memory, I/O on single chip. Self-contained system, lower power, cost-effective for embedded applications.

Microprocessor: Only CPU, requires external memory and I/O. More powerful, flexible, used in computers and high-performance systems.

GPIO (General Purpose Input/Output) pins can be configured as input or output for interfacing with external devices.

Configuration: Direction register (input/output), pull-up/pull-down resistors, drive strength, interrupt capabilities. Set via hardware registers.

PWM (Pulse Width Modulation) varies duty cycle of digital signal to control average power.

Applications: Motor speed control, LED brightness, analog voltage generation (with low-pass filter), servo control, switching power supplies.

ADC (Analog-to-Digital Converter) converts analog voltage to digital value.

Key specs: Resolution (8/10/12-bit), sampling rate, reference voltage, input range. Configure channel, start conversion, read result register.

• Active: CPU and peripherals running, highest power
• Sleep: CPU stopped, peripherals active, quick wake-up
• Deep sleep: Most peripherals off, slower wake-up
• Standby: Minimal power, only wake-up sources active

Watchdog timer resets the system if not refreshed within timeout period, preventing system hangs.

Implementation: Periodic "kick" in main loop or timer interrupt. Critical for safety systems. Some have window watchdog (too early refresh also resets).

Memory-mapped: I/O registers in memory address space, accessed like normal memory. Common in ARM processors.

Port-mapped: Separate I/O address space, special instructions (IN/OUT). Used in x86 architecture. Most microcontrollers use memory-mapped.

Hardware timers count clock pulses, generating interrupts or events at specified intervals.

Applications: Delays, PWM generation, input capture, event counting, system tick for RTOS, timeout detection, periodic tasks.

RTOS (Real-Time Operating System) provides deterministic task scheduling with guaranteed response times.

Use when: Multiple concurrent tasks, timing-critical operations, complex applications, need for synchronization primitives. Examples: FreeRTOS, ThreadX, µC/OS.

• Preemptive: Higher priority task interrupts lower priority
• Cooperative: Task voluntarily yields control
• Time-slicing: Equal priority tasks share CPU time
• Rate Monotonic: Fixed priority based on period
• Earliest Deadline First: Dynamic priority based on deadlines

Priority inversion occurs when high-priority task waits for resource held by low-priority task, while medium-priority task runs.

Solutions: Priority inheritance (temporarily boost low-priority task), priority ceiling (elevate task to highest priority of shared resources).

Semaphore: Counting mechanism for resource access, can be binary or counting.

Mutex: Binary semaphore for mutual exclusion, often with ownership and priority inheritance.

Message Queue: FIFO buffer for inter-task communication, passes data not just synchronization signals.

Deadlock occurs when tasks wait for each other's resources indefinitely.

Prevention: Resource ordering (acquire in same order), timeout mechanisms, avoid nested locks, use higher-level abstractions like channels.

Each task has dedicated stack space. Overflow corrupts other memory or causes crashes.

Protection: Stack canaries, stack high water mark monitoring, MPU protection, proper stack size calculation including interrupt nesting.

Interrupts pause normal program execution to handle urgent events. CPU saves context, jumps to interrupt service routine (ISR).

Types: External (GPIO), internal (timers, UART), software interrupts. Priority levels determine nesting behavior.

• Keep ISRs short and fast
• Avoid blocking operations (malloc, printf, delays)
• Use volatile for shared variables
• Clear interrupt flags
• Defer complex processing to main loop or tasks
• Be careful with reentrant functions

Latency: Time from interrupt signal to ISR start. Affected by instruction completion, interrupt disable periods.

Jitter: Variation in latency. Critical for real-time systems. Minimize by reducing critical sections, using proper priorities.

Race conditions occur when shared data is accessed simultaneously by main code and interrupts.

Solutions: Disable interrupts briefly, atomic operations, use volatile keyword, message passing instead of shared variables.

I2C (Inter-Integrated Circuit) is 2-wire serial protocol: SDA (data), SCL (clock). Multi-master, multi-slave with 7-bit addressing.

Features: Start/stop conditions, ACK/NACK, pull-up resistors required, speeds up to 3.4 Mbps. Good for sensor communication.

SPI: 4-wire (MOSI, MISO, SCK, CS), faster, full-duplex, simple hardware, no addressing.

I2C: 2-wire, multi-master, addressing scheme, more complex protocol, built-in flow control. Choose SPI for speed, I2C for simplicity.

UART: Asynchronous serial communication, start/stop bits, configurable baud rate, parity.

USART: UART + synchronous mode with clock signal. More flexible, can operate in UART mode for compatibility.

CAN (Controller Area Network) is robust, multi-master protocol with message prioritization based on arbitration.

Features: Differential signaling, error detection/correction, automatic retransmission. Widely used in automotive, industrial control.